As is known in the art, a computer system generally includes a central processing unit (CPU), which is referred to herein simply as “processor”, a memory system, a cache system, and an I/O system. These systems are coupled together through various busses. The CPU, which may be constructed of a single chip or multiple chips, also generally includes an arithmetic logic unit (ALU), floating point unit (FPU), a program counter, a plurality of high speed memory locations known as registers, a memory controller for reading from and writing to memory, and control logic for fetching instructions from memory. Moreover, the CPU includes circuitry for executing the instructions fetched from memory.
Once a computer system has been designed, system designers need to verify the operation of the CPU. The verification is performed to ensure that the CPU operates as designed. Furthermore, verification is performed to ensure that the CPU interfaces properly with each of the elements described above. As can be appreciated, this process of verifying the design of a central processing unit (CPU) is important in developing a successful microprocessor product.
In order to verify that each element of the newly designed computer system functions properly, system verification engineers create a computer model of the CPU chip. In addition, models are created for each of the subsystem elements that provide stimulus to the CPU model. Each element in the system has a unique model which represents its operation in the form of its response to input stimulus. The models can be created using specialized programming languages developed solely for that purpose, or they can be created using general purpose programming languages, such as the C programming language or the C++ programming language.
Since the CPU is the heart of most computer systems, the model of the CPU is typically the most complex and sophisticated. In order to properly verify the functionality of the CPU, various stimuli are applied to the model. The response of the model to the various stimuli is recorded and analyzed by a verification engineer.
In order to sufficiently test the CPU, the model must be exercised as extensively as possible. One prior art method of testing a CPU design involves manually written tests. These tests are typically written by system verification engineers, who select the type of stimuli to be applied to the CPU model. These manually written tests include only the test stimuli, which the engineer believes are appropriate for the CPU model. In addition to creating the test stimulus program, the engineer also needs to design a method of checking the results generated by the CPU model in response to the applied stimulus.
Another prior art method of creating verification test programs involves the use of random test file generators. A random test file generator is a program that has knowledge of each possible command that can be executed by the CPU. The random test file generator also has knowledge of possible delays or hand shaking methods that are used when the CPU communicates with other subsystems. The random test file generator randomly selects, from each of the parameters of which it has knowledge, operations to be performed by the CPU model, thereby creating randomly generated test files or test programs that may be applied to the CPU model.
One advantage of using random test generators is that the random test generators tend to provide far more complete tests in a shorter time frame than the manually written test programs described previously. In addition, random test generators can create combinations of various stimuli that a system verification engineer may overlook or be unaware of.
There are various ways in which the test files created by random test generators may be used to verify designs. One method is to apply the same test files to the design to be verified and an abstract representation of the design known as the reference model. The results of each test file application are recorded and manually compared. Any mismatches in the recorded results are manually flagged as problems and used to further diagnose the design.
Prior art methods of checking a design against a reference model have been performed manually by a verification engineer, which tended to make the comparison process labor intensive and expensive.
In a perfect world, testcases would not fail due to incorrect values. However, in the real world, since testcases can fail due to incorrect values, the debugging of testcases is an important component of the design verification process.
For example, a load instruction may be executed correctly. However, if the address register did not contain a value that a random code generator expected, a translation lookaside buffer (TLB) miss fault can occur. The verification engineer must then manually search the instruction code flow in an iterative fashion to determine the most recent instruction that affects the value. This process is repeated until the origin of the value is determined.
When an incorrect value causes a randomly-generated testcase to fail, a verification engineer is required to determine what exactly caused the incorrect value. The verification engineer typically employs the process of backtracing to determine the cause of the incorrect value.
Backtracing is the manual process of going through the flow of instructions to determine where values originate. This backtracing process is an iterative process that goes back through the instruction flow to find the most chronologically recent instruction that affect a value in question. The iterative process is repeated until the source of a particular value is located.
As can be appreciated, when many instructions are present, this iterative process is time consuming and labor intensive. Accordingly, prior art methods for manually performing backtracing are severely limited in terms of efficiency.
Based on the foregoing, there remains a need for an automated method and system for backtracing of instruction parameters from specified instruction in test cases that overcomes the disadvantages of the prior art as set forth previously.